Swing Restored Pass-transistor Logic (SRPL), a high speed, low power logic circuit technique for VLSI applications is described. By the use of a pass-transistor network to perform logic evaluation, and a latch type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance.
Swing Restored
Pass Gate Logic Results Research Logic Families Notes winspice EEPTL Electric
PPL achieves a performance advantage using complementary logic trees, and cross coupling to pull up or pull down devices, which recover full rail voltage. By doing so, total device count, load circuit capacitance, and power consumption is reduced [2,4,7-10]. (cc) photo by Metro Centric on Flickr (cc) photo by Franco Folini on Flickr (cc) photo by jimmyharris on Flickr winspice (cc) photo by Metro Centric on Flickr Swing restored pass-transistor logic (SRPL), a high-speed, low-power logic circuit technique for VLSI applications, is described. By the use of a pass-transistor network to perform logic evaluation and a latch-type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance. An SRPL based multiply and ac-cumulate circuit for multimedia applications is implemented in double metal 0.4 rm CMOS technology. The gate inputs are of two types:
pass variables that are connected to
the drains of the logic network transistors and control variables that
are connected to the gates of the transistors. The generic SRPL gate consists of
two main parts -a complimentary output pass-transistor logic network that is constructed of n-channel devices
and a latch-type swing restoring circuit
consisting of two cross-coupled
CMOS inverters. The logic net-work has the ability to implement any random Boolean logic function for instance, shows the implementation of an SRPL full adder. The complimentary outputs of the pass-transistor logic network are restored to full swing by the swing restoration circuit. Electric Winspice Energy
Economized Pass
Transistor Logic Push Pull Pass
Transistor Logic notes Lean Generated
Pass Gate logic pptl Sarah Jane T. Arbitrario SRPGL: Energy economized pass-transistor logic as "EEPL") which includes a pass-transistor logic (PL) circuit (or, a functional block) 10 for performing logical ANDing and NANDing functions of two inputs "A" and "B" and a level restoration circuit 50 having energy economized configuration. Electric . Here, the output inverters are cross-coupled to a latch structure which performs swing restora¬tion and output buffering at the same time. Note that the pull-up PMOS transistors are not required anymore and that the output nodes of the NMOS network are also the gate outputs. Electric winspice truth table
Swing Restored
Pass Gate Logic Results Research Logic Families Notes winspice EEPTL Electric
PPL achieves a performance advantage using complementary logic trees, and cross coupling to pull up or pull down devices, which recover full rail voltage. By doing so, total device count, load circuit capacitance, and power consumption is reduced [2,4,7-10]. (cc) photo by Metro Centric on Flickr (cc) photo by Franco Folini on Flickr (cc) photo by jimmyharris on Flickr winspice (cc) photo by Metro Centric on Flickr Swing restored pass-transistor logic (SRPL), a high-speed, low-power logic circuit technique for VLSI applications, is described. By the use of a pass-transistor network to perform logic evaluation and a latch-type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance. An SRPL based multiply and ac-cumulate circuit for multimedia applications is implemented in double metal 0.4 rm CMOS technology. The gate inputs are of two types:
pass variables that are connected to
the drains of the logic network transistors and control variables that
are connected to the gates of the transistors. The generic SRPL gate consists of
two main parts -a complimentary output pass-transistor logic network that is constructed of n-channel devices
and a latch-type swing restoring circuit
consisting of two cross-coupled
CMOS inverters. The logic net-work has the ability to implement any random Boolean logic function for instance, shows the implementation of an SRPL full adder. The complimentary outputs of the pass-transistor logic network are restored to full swing by the swing restoration circuit. Electric Winspice Energy
Economized Pass
Transistor Logic Push Pull Pass
Transistor Logic notes Lean Generated
Pass Gate logic pptl Sarah Jane T. Arbitrario SRPGL: Energy economized pass-transistor logic as "EEPL") which includes a pass-transistor logic (PL) circuit (or, a functional block) 10 for performing logical ANDing and NANDing functions of two inputs "A" and "B" and a level restoration circuit 50 having energy economized configuration. Electric . Here, the output inverters are cross-coupled to a latch structure which performs swing restora¬tion and output buffering at the same time. Note that the pull-up PMOS transistors are not required anymore and that the output nodes of the NMOS network are also the gate outputs. Electric winspice truth table
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