- Different technologies by year:
- 10 µm — 1971
- 3 µm — 1975
- 1.5 µm — 1982
- 1 µm — 1985
- 800 nm — 1989
- 600 nm — 1994
- 350 nm — 1995
- 250 nm — 1997
- 180 nm — 1999
- 130 nm — 2002
- 90 nm — 2004
- 65 nm — 2006
- 45 nm — 2008
- 32 nm — 2010
- 22 nm — 2012
- 14 nm — 2013
- 10 nm — est. 2015
- 7 nm — est. 2017
- 5 nm — est. 2019
What is meant by different VLSI technologies like 45nm ,65nm etc.?
In simple words, we can say all these different technologies based on the minimum gate length of the transistors which we use in these technologies...
For example, when we say 65nm technology, that means the transistor gate length in this technology is 65nm..and so on for corresponding technologies..
This is the general definition we follow..but the minimum length can be a bit small than the technology node value..say 60nm in 65nm technology node...
For example, when we say 65nm technology, that means the transistor gate length in this technology is 65nm..and so on for corresponding technologies..
This is the general definition we follow..but the minimum length can be a bit small than the technology node value..say 60nm in 65nm technology node...
To expand it just a tiny bit, aside from the gate width, when you talk about a technology node, such as 45 nm, you immediately allow the designers to compute certain things, like: the dynamic power consumption is CV^2f. Right there, "C" is the representative capacitance of that technology node. Also, the designer can look up the FO4 delay of that node to scale, say, a 45nm design down to a 65nm design by simply scaling the FO4 delays of the two nodes ...
Also, INTEL's tick-tock methodology works as tick (re-design) and tock (adapt a previous design to a lower node). The adaptation is done by using the metrics to re-calculate the new node's parameters by comparing the two nodes ...
In summary, when you mention a node, like, 45 nm, you are referring to a bunch of characteristic values. It refers to the smallest possible feature size.
In advanced CMOS technologies, e.g. 32nm, 28 nm, etcetera, these numbers usually refer to 1/2 the contacted pitch of the DRAM, which is also 1/2 the pitch of the first level of metalization (the closest to the silicon substrate). It is close to the printed gate length of transistors, but not identical. Have a look at the International Technology Roadmap of Semiconductors (ITRS). For instance, this is the link to the Executive Summary:
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