Mentor Graphics University Design Contest 2013

Call for Participationwww.mentor.com

This is the Fourth Mentor Graphics University Design contest 2013 in India. The focus of this contest is to provide an opportunity for engineering students to showcase their technical talent and competency using Mentor Graphics tools. We expect to grow this contest with increased representation & participation, and draw maximum number of contestants for the contest

Mentor Graphics University Design Contest?

This competitive design contest is aimed at :

• Provide an opportunity for engineering students from different technology streams to participate in the contest and demonstrate their technical capabilities, problem solving, project management and design skills in a contest against their peers.
• Provide all participants with new perspectives on how design teams from different disciplines and different regions of the country approach a common design problem.
• Provide engineering students with a chance to meet experts to showcase and present their ideas, and also network with fellow participants to discuss newer ideas of working on a project.

Project Proposal - The Design Problem

The primary motivation behind coming up with this problem was to give you a hands-on perspective on ‘high performance computing’, where-in you would learn what it takes to offload a computational task to an FPGA. Sure, there are challenges in creating an RTL that maps optimally to a specific FPGA architecture, but the performance advantage delivered by such massively parallel implementation clearly outweighs the sequential implementation that runs as a software application on a standard CPU.

In a way, such a reconfigurable (FPGA) implementation lets you design your own ‘custom’ processor that has plenty of registers and memory (cache) at its disposal, with instructions hardcoded as parallel dedicated circuits.

Coming to the contest problem, there’s one primary task that you will have to accomplish. The basic requirement is to create a functionally correct RTL solution that fits into Xilinx’s Spartan 3A FPGA. However the challenge is to accomplish this in as less number of clock cycles as possible, consuming minimum FPGA resources while achieving maximum operating frequency.

The Contest Design & Structure

The contest follows a three stage process. Each stage will focus on communicating the team's ideas through a different channel, as follows:

• Teams will submit a short project paper (10 pages maximum) describing their solution to the project proposal. University Design Contest Technical committee will review and evaluate all the submissions. A maximum of 10 teams will be selected for the next stage.
• Shortlisted teams will be expected to send a presentation outlining the entire description. The proposed solution will be reviewed by the University Design Contest Technical committee. The Technical committee will select 5 teams for the final selection/ranking.
• The 5 finalists will be rated based on their proposed solution/design to the technical committee. Based on the criteria below, the competition judges will rank and identify an overall winner of the competition and one runner-up team.

Awards

The top three winners of the University Design Contest will earn a Certificate of Recognition. There will be one Winner team followed by two runner-up teams.

The winning team will be awarded a cash prize of US$3000.
1st Runner-up – US$2000.
2nd Runner-up – US$1000.