Synopsys provides universities with access to comprehensive curricula for Bachelor and Master Programs in microelectronic design and EDA development. We work closely with our
Curricula Advisory Board, a team of academic experts, to advise on the overall program content and to review and provide feedback on the materials.
Each full-semester course contains 15 weeks of material including syllabus, lectures, labs, homework and exams. Synopsys tools are applied in the labs for a thorough and practical understanding of theoretical concepts introduced in each course. Professors at member universities may use these course materials to implement a new course or to supplement content in an existing course.
All courseware described below may be downloaded from the Synopsys University Program
Member Only website (requires SolvNet ID and password). If your university is not yet a member of the Synopsys University Program and you would like to apply, please contact the
program administrator for your region.
Curriculum Support Modules: Workshops and Lectures |
- Verification:
- SystemVerilog/Verification Methodology Manual (VMM)
- SystemVerilog Verification Tutorial (SFSU) - New!
- Universal Verification Methodology -New!
- Verilog HDL Basics
- TCAD:
- TCAD Course
- TCAD for VLSI Design
- TCAD Short Course
- TCAD Quick Start Guide
- Other:
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- Implementation:
- 90nm Digital Design Workshop
- ASIC Design Flow Tutorial Using Synopsys Tools
- Digital Design Flow Based on PowerPC 405 Processor
- Full Custom IC Design Flow Using Synopsys Custom Tools (SFSU)
- IC Synthesis Based on ARM Cortex-MO DesignStart Processor - New!
- IC Synthesis Based on DesignWare ARC 600 Core - New!
- Software Methodology Using Custom Designer
- Synopsys Design Flow Tutorial
- Synopsys IC Design Flow Based on 90nm Generic Library (SAED 90nm EDK)
- Synthesis Basics - New!
- UPF Workshop
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Short Lectures/Labs |
- Circuit Simulation:
- Circuit Simulation: Transient Analysis
- Techniques for Circuit Simulation
- Thermal and Electro-Thermal Simulation: Achievements and Trends
- Low Power Design:
- Low Power Methodology Manual for 90nm
- Low Power Methodology Manual for 32/28nm - New!
- Subthreshold Design and Implementation (RIT)
- Verification Methodology Manual for Low Power (VMM-LP)
- OpenSPARC:
- Multi-threaded SPARC core verification using SystemVerilog Testbench
- Synthesizing 64-bit OpenSPARC multi-threaded core on FPGA with Synopsys Synplify tool chain
- Synthesizing a Design Using the 90nm Technology Library
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- Other:
- Addressing Process Variations and Patterning Issues in VLSI Designs (UCLA)
- Advanced RTL Verification Techniques
- Basic Perl Programming
- Design Methods of Nanoscale Memories
- Design Methods of Nanoscale Sigma-Delta Modulators
- Embedded Systems Design
- How to Create an Interoperable PDK
- Introduction to Verilog HDL - Updated!
- Logic Simulation with Consideration of Destabilizing Factors
- Nanoscale Low Power Digital Standard Cell Library Tutorial
- Physical Verification Runset Development
- Power-Performance Optimization of Digital Circuits and Systems
- Process Variation Aware Design
- Sequential Elements - Updated!
- Signal and Power Integrity: Current State and New Approaches
- Statistical Techniques for Timing Analysis: Current State and Trends
- TCAD Microelectronic Labs (IIT)
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