Sunday, 29 December 2013
Full Time Custom Design Of A Logic Inverter
4B7 VLSI Design, Technology and CAD
Resource Page
What's New
- Latest Developments in microelectronics
- List of names and lab experiments for 2013
- ITRS Roadmap for Semiconductors
An assessment of global semiconductor technology requirements
Contents
- Introduction; lectures and coursework
- The introductory lecture
- Selected lecture material
- Derivation of noise margins for CMOS inverter (.pdf file - for reference only)
- Stick diagrams handout with colour annotations (.pdf file)
- Coursework
- Examples Sheet and solutions
- Teaching software:-
- EDEC - MOS transistor operation
- Educational Java applets
- Full custom design of a logic inverter
- Useful articles
- Other Web sites
- Latest Developments in microelectronics
- Virtual SEM web site
- SEM images of ICs
Introduction
Link to local copy of Department Course SummaryThe aim of module 4B7 (VLSI Design, Technology and CAD) is to describe the design, technology and manufacture of MOS integrated circuits and future nanoscale electron devices. It will provide a firm foundation for those wishing to pursue careers in applications or in research/development in the field of semiconductor devices/circuits.
LECTURES
VLSI Design and CAD of MOS Integrated Circuits (6L, Dr D.M. Holburn)
- Challenges of designing complex CMOS circuits.
- Hierarchical design, layout and design rules.
- Parasitic elements, simulation and verification.
- VLSI circuit techniques.
- Energy conservation in IC design
- Case studies: typical IC designs - Flash memory.
- Challenges of VLSI technology.
- Example of CMOS: fabrication
- Case study of i.c. technology.
- Recent developments and future prognosis.
- 2 hour laboratory experiment illustrating VLSI design, with 4-side report
- 2 hour hands-on scanning electron microscope examination of devices and circuits, with 4-side report
The Introductory lecture:
- Slides (converted from Powerpoint) and Text of talk _
- Microscope images of Intel microprocessors (slow site)
Other selected lecture material
Please click to open these in a new browser window. The Adobe Acrobat plugin is required for the .pdf files.
| Section and Title |
MESP
course |
4B7
(2013) |
| Introduction - The Challenges of VLSI Design | YES | |
| Sections 1-3 - The MOS Transistor (includes links to interactive models) | YES | |
| Section 4 - The Transmission Gate | YES | |
| Section 5 - Deleted | ||
| Section 6 - Design Rules (includes: Scaling in VLSI Design) | YES | |
| Section 7 - Circuit Extraction | YES | |
| Section 8 - Advanced Design Verification (MESP course only) | YES | |
| Section 9 - SPICE - Circuit Simulator (MESP course only) | YES | |
| Section 10 - Linear Circuit Design | YES | |
| Supplement - Integrated CMOS Voltage Reference | YES | |
| Section 12 - The logic abstraction | YES | |
| Section 13 - Deleted - in Prof Kelly/Prof Udrea's section | ||
| Section 14 - I/O Pads and Pad Drivers | YES | |
| Section 15 - Energy Conservation in VLSI Design | YES | |
| Section 16 - Test and Testability in VLSI (MESP course only) | YES | |
| Sections 17-19 - Deleted | ||
| Section 20 - Design Styles in VLSI (MESP course only) | YES |
Examples
- Examples Sheet - problems in VLSI Design (Acrobat PDF version)
- Solutions for Examples Sheet (Acrobat PDF version)
NB Questions 11 and 12 were not covered this yearIndividual solutions: these have been scanned in at 100 dpi and should be readable with a display of 800 x 600 pixels or greater. Click any of the hyperlinks below to see the corresponding part of the crib in a new browser window. Please do not send these images to the Department printers!
Question 1 | 2 | 3 | 4 | 5 | 6 | 7 | 7 cont | 8 | 8 cont | 9 | 10 | 10 cont |
Lab Coursework
- Coursework administration (2012-13)
Electrical Characterisation of Ring Oscillator
- Browsable version of the lab-sheet for the experiment (Acrobat pdf)
- Model write-up for the experiment (Acrobat pdf version) - coming in a day or so
(indicative only - the experiment is updated each year)
SEM Examination of Ring Oscillator
- Browsable version of the lab-sheet for the experiment (Acrobat pdf)
- Model write-up for the experiment (Acrobat pdf version) - coming in a day or so
(indicative only - the experiment is updated each year)
Teaching Software
Electronic Design Education Consortium
MOS Transistor operation
This is a member of a suite of more than a hundred applications produced some years ago by the Electronic Design Education Consortium to illustrate various devices, circuits, methods and design techniques in electronics. The module illustrating MOS transistor operation was used in the second of the 4B7 Digital Circuits lectures. Unfortunately licensing restrictions at the time prevented us from making this available as a downloadable archive. This has now been resolved. Read on for details of how to access a web-based version.
Click on the EDEC button above for more details of the EDEC Consortium's activities (coming soon, when the link can be found).
This suite is now available on the web in archive form, provided courtesy of the Jorum Repository. While direct access to Jorum is restricted to staff only, even for browsing, under the terms of the Jorum Repository, it is permissible for registered members to download archives and host them for legitimate teaching purposes. It has now been downloaded as an archive and re-installed on a CUED server. The link given above provides a temporary interface to most of the functionality.
If your computer is on a .cam.ac.uk subnet, you should have direct access; otherwise you will need your CUED PIN (in due course Raven password authentication will be introduced). You will need to download the Macromedia Authorware Player plugin for your browser. This has worked fine with Microsoft's Internet Explorer, but with Firefox it is necessary to download the plug-in manually, then install it with the browser shut down..
If you tried before and were prevented from access by Jorum's access conditions, please try again 5 Feb 2009.
Educational Java applets
This applet is a slightly simplified version of the EDEC MOSFET model above. Try it! (But please note that it is a project under development, and may be withdrawn for update, etc).These are a couple of examples of applets held in an archive at Dept of EE, SUNY, Buffalo USA. There is a longer list of other applets relating to materials, microelectronics, etc
The following two links no linger seem to work following a reorganisation at the Ecole Nationale Supérieure des Télécommunications web site. They have been left in the hope that the very useful applets to which they used to point might soon be found!
These two were found not to work reliably with all the latest IE and Netscape Navigator browsers.
However, Netscape Navigator 3 (also available from the Sunsite software archive at Imperial College) has appeared to be suitable for them.
Full custom design of a logic inverter
A Powerpoint animation depicting key stages in the full-custom design of a logic inverter was shown during a lecture - refer to section 6.0. This represents a design carried out for an n-well process, in which the substrate is of p-type semiconductor, requiring an n-well to be implanted in which to fabricate the p-channel transistors. You can view the Powerpoint animation on your browser:- Here you will find the presentation saved as html
(Note: in 2005 this appears to be causing problems now with IE6. If so, try the Powerpoint file below) - Here is the original Powerpoint .ppt file
Click here for the set of images with descriptive text optimised for 800 x 600.
Click the thumbnail if you want to see the full-size image.
 | P-well (diagonal brown shading). The process illustrated is a p-well process. This uses an n-type substrate in which the p-channel transistors will be fabricated directly. The brown shaded region is implanted with p type dopants to form a p-well, in which the n-channel transistors can be fabricated. |
 | P-well with active regions (green cross-hatching). The active regions indicate zones where the transistor channels will lie. These regions are protected by a thin coat of silicon nitride while surrounding areas have a thick layer of field oxide grown upon them. The smaller 'active' squares at extreme top and bottom will provide low-resistance connections to the substrate and the p-well, required to ensure proper isolation between devices. |
 | Polysilicon gate electrodes and polysilicon interconnect (red). The single vertical strip of polysilicon crossing the two active regions provides the two gate electrodes and an electrical connection between them, and a route by means of which the input signal may be brought into the cell across the power rails (yet to be provided at top & bottom). The polysilicon also helps delimit the regions implanted p+ and n+. |
 | P+ and N+ implants (yellow and green). These determine the positions of the source and drain in the corresponding devices. N-channel transistors require n+ implants to form their drain and source, while p-devices require p+ implants. Note that the polysilicon gate screens the channel region which does not receive these implants. |
 | Contact windows (black). These indicate regions where an etch process cuts through the insulating layers, linking metal to semiconductor or metal to polysilicon. |
 | Metal 1 (dark blue) furnishes the power rails (Vdd and Vss at top & bottom respectively, and a link between the two MOSFET drains, from which the output is coupled to points at the top and bottom of the cell by means of a vertical strip of polysilicon. |
Useful Articles
Let me know if you discover any interesting articles that could be referenced here ..Nanoscale CMOS - No Successor in Sight! (Powerpoint presentation) - Yuan Taur
There is no credible candidate on the horizon that promises to supplant CMOS ULSI ..
Prospects of Si ULSI Devices for the Next Ten Years (.pdf file) - Yuan Taur, University of California (biographical details)
After three decades of continued growth, the microelectronic industry is facing unprecedented challenges in the next ten years. CMOS scaling, the engine that delivered higher density and performance and at the same time lower power and cost in the past, will encounter fundamental limiting factors and could be running out of steam below 50 nm dimensions ..
After three decades of continued growth, the microelectronic industry is facing unprecedented challenges in the next ten years. CMOS scaling, the engine that delivered higher density and performance and at the same time lower power and cost in the past, will encounter fundamental limiting factors and could be running out of steam below 50 nm dimensions ..
CMOS design near the limit of scaling (.pdf file) - Yuan Taur (2002) - biographical detailsThis paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length.
See how a silicon chip is made - Sematech (currently inactive - 2005)
How chips are made - Intel
International Technology Roadmap for Semiconductors (ITRS)
The International Technology Roadmap for Semiconductors (ITRS) is an assessment of semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It represents a very dense set of data. To start with, explore the Executive Summary for the current year. As you find aspects that interest you, you can investigate the more detailed sections.
The International Technology Roadmap for Semiconductors (ITRS) is an assessment of semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It represents a very dense set of data. To start with, explore the Executive Summary for the current year. As you find aspects that interest you, you can investigate the more detailed sections.
The Future of Integrated Circuits (includes archive documents from the mid-60's) for 2005
A roundup of progress in technology during the 60's and the emergence of Gordon Moore's Law for Intel microprocessor chips
Beyond the conventional transistorThis paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials.A roundup of progress in technology during the 60's and the emergence of Gordon Moore's Law for Intel microprocessor chips
Other Web Sites
- Link to ITRS Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors (ITRS) is an assessment of semiconductor technology requirements: its objective is to promote advancement in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It is sponsored by a an international consortium of semiconductor manufacturing associations. - Cambridge Silicon Radio (CSR)
- Tour IBM's 300mm IC foundry (Windows Media Player)
Latest Developments
- Boffins pave way for 400x rise in CPU transistor count
Engineers at the University of California, Berkeley, announced today (Monday, Nov. 22) the creation of a new type of semiconductor transistor so small that a single computer chip can hold 400 times more of the devices than ever before. - Revolutionary Transistor Design Turns the Silicon World on End
Using a revolutionary design, researchers at Bell Labs have produced the world's smallest transistor with equipment available in today's manufacturing facilities. This new design may help silicon chips continue their march toward smaller and smaller dimensions, and it has the potential added benefit of nearly doubling the processing speeds of some chips. - IBM's SiGe Technology for Telecommunications and Mixed Signal Applications
Recent developments in bipolar technology are leading to even faster bipolar devices. Research at IBM has shown that fabricating bipolar devices from silicon with a small proportion of germanium added gives a significant speed enhancement. It's fascinating to note that the earliest transistors in the late 40s/early 50s were manufactured solely from germanium, but until this latest discovery germanium technology had been all but abandoned! The resultant HBT (Heterojunction Bipolar Transistor) is a supercharged device, operating at up to 120 GHz, many times faster than the best silicon-only devices that can now be made.
SEM images of microelectronic circuits
Click the thumbnail to see the full size image:- | CMOS 2 input NOR gate with passivation and upper metal layers removed (3 micron CMOS) |
 | A portion of a ring oscillator based on the CMOS 2-input NOR gate |
 | A binary counter / frequency divider implemented on the same chip |
 | The view seen by a CCD camera placed in the SEM's specimen chamber. Above, the curved conical feature is the magnetic objective lens. The electron beam is directed vertically down and is focussed on the specimen (a sliver of silicon wafer), fixed to a circular specimen stub. |
 | Part of the IC studied in the SEM by last year's 4B7 group |
 | The same area with a small cut machined using ion beam milling |
 | A close-up of the machined cut. In the full-size image you can clearly see the various semiconductor layers in section. |
 | A mystery object ... |
 | A slightly different view ... |
 | And another ... |
| The collage may help you identify this everyday item ... |
Hit Counter
This set of pages has been accessedUpdated 26 March, 2013
Contact Information
HSPICE Commands
Input Netlist File (<design>.sp)
Star-Hspice operates on an input
netlist file and stores results in either an output listing file or a graph
data file. The Star-Hspice input file, with the name <design>.sp,
contains the following:
·
Design netlist (with subcircuits and macros, power supplies, and so on)
·
Statement naming the library to be used (optional)
·
Specification of the analysis to be run (optional)
·
Specification of the output desired (optional)
Input netlist and library input
files are generated by a schematic netlister or with a text editor.
Statements in the input netlist
file can be in any order, except that the first line is a title line, and the
last .ALTER submodule must appear at the end of the file before the .END
statement.
Input
Line Format
·
The input netlist file cannot be in a packed or compressed format.
·
The Star-Hspice input reader can accept an input token, such as a
statement name, a node name, or a parameter name or value. A valid string of characters
between two token delimiters is accepted as a token. See “Delimiters” below.
·
Input filename length, statement length, and equation length are limited
to 256 characters.
·
Upper and lower case are ignored, except in quoted filenames.
·
A statement may be continued on the next line by entering a plus (+)
sign as the first nonnumeric, nonblank character in the next line.
·
Comments are added at any place in the file. Lines beginning with an asterisk
(*) are comments.
·
Place a comment on the same line as input text by entering a dollar sign
($), preceded by one or more blanks, after the input text.
·
An error is issued when a special control character is encountered in
the input netlist file.
Names
·
Names must begin with an alphabetic character, but thereafter can
contain numbers and the following characters: ! # $ % * + - / < > [
] _
·
Names are input tokens that must be preceded and followed by token delimiters.
See “Delimiters” below.
·
Names can be 1024 characters long.
·
Names are not case sensitive.
Delimiters
·
An input token is any item in the input file recognized by Star-Hspice.
Input token delimiters are: tab, blank, comma, equal sign (=), and parentheses “(
)”.
·
Single or double quotes delimit expressions and filenames.
·
Element attributes are delimited by colons (“M1:beta”, for example).
·
Hierarchy is indicated by periods. For example, “X1.A1.V” is the V node on
subcircuit A1 of circuit X1.
Nodes
·
Node identifiers can be up to 1024 characters long, including periods
and extensions.
·
Leading zeros are ignored in node numbers.
·
Trailing alphabetic characters are ignored in node numbers. For example,
node 1A is the same as node 1.
·
A node name can begin with any of the following characters: # _ ! %.
·
Nodes are made global across all subcircuits by a .GLOBAL statement.
·
Node 0, GND, GND!, and GROUND all refer to the global Star-Hspice ground.
Instance
Names
·
The names of element instances begin with the element key letter (for example,
M for a MOSFET element, D for a diode, R for a resistor, and so on), except in
subcircuits.
·
Subcircuit instance names begin with “X”. (Subcircuits are sometimes called
macros or modules.)
·
Instance names are limited to 1024 characters.
·
.OPTIONS LENNAM controls the length of names in Star-Hspice printouts (default=8).
Numbers
·
Numbers are entered as integer or real.
·
Numbers can use exponential format or engineering key letter format, but
not both (1e-12 or 1p, but not 1e-6u).
·
Exponents are designated by D or E.
·
Exponent size is limited by .OPTIONS EXPMAX.
·
Trailing alphabetic characters are interpreted as units comments.
·
Units comments are not checked.
·
.OPTIONS INGOLD controls the format of numbers in printouts.
·
.OPTIONS NUMDGT=x controls the listing printout accuracy.
·
.OPTIONS MEASDGT=x controls the measure file printout accuracy.
·
.OPTIONS VFLOOR=x specifies the smallest voltage for which the value will
be printed. Smaller voltages are printed as 0.
Parameters
and Expressions
Use the PAR(expression or
parameter) function to evaluate expressions in output statements.
.TITLE
Statement
The .TITLE statement resets the
title printed on each subsequent print, plot, probe, or graph statement.
.GLOBAL
Statement
The .GLOBAL statement is used
when subcircuits are included in a netlist file. This statement assigns a
common node name to subcircuit nodes. Power supply connections of all
subcircuits are often assigned using a .GLOBAL statement. For example, .GLOBAL
VCC connects all subcircuits with the internal node name VCC.
Comments
An asterisk (*) or dollar sign
($) as the first nonblank character indicates a comment statement.
Syntax
* <comment on a line
by itself>
or
<HSPICE
statement> $ <comment following HSPICE input>
Node Names
Nodes are the points of
connection between elements in the input netlist file. In Star-Hspice, nodes
are designated by either names or by numbers. Node numbers can be from 1 to
999999999999999; node number 0 is always ground. Letters that follow numbers in
node names are ignored. Node names must begin with a letter or slash (/) and
are followed by up to 1023 characters. In addition to letters and digits, the
following characters are allowed in node names:
+ plus sign
- minus sign or hyphen
* asterisk
/ slash
$ dollar sign
# pound sign
[ ] left and right square brackets
! exclamation mark
< > left and right angle brackets
_ underscore
% percent sign
Braces, “{ }”, are allowed in
node names, but Star-Hspice changes them to square brackets, “[ ]”.
The following are not allowed in
node names:
( ) left and right parentheses
, comma
= equal sign
‘ apostrophe
blank space
.ALTER Statement
You can use the .ALTER statement
to rerun a simulation using different parameters and data.
Print and plot statements must be
parameterized to be altered. The .ALTER block cannot include .PRINT,
.PLOT, .GRAPH or any other I/O statements. You can include all analysis
statements (.DC, .AC, .TRAN, .FOUR, .DISTO, .PZ, and so on) in only one .ALTER
block in an input netlist file, but only if the analysis statement type
has not been used previously in the main program. The
.ALTER sequence or block can
contain:
·
Element statements (except source elements)
·
.DATA statements
·
.DEL LIB statements
·
.INCLUDE statements
·
.IC (initial condition) and .NODESET statements
·
.LIB statements
·
.MODEL statements
·
.OP statements
·
.OPTIONS statements
·
.PARAM statements
·
.TEMP statements
·
.TF statements
·
.TRAN, .DC, and .AC statements
Syntax
.ALTER <title_string>
Example 2
FILE2: ALTER2.SP CMOS INVERTER USING
SUBCIRCUIT
.OPTIONS LIST ACCT
.MACRO INV 1 2 3
M1 3 2 1 1 P 6U 15U
M2 3 2 0 0 N 6U 8U
.LIB 'MOS.LIB' NORMAL
.EOM INV
XINV 1 2 3 INV
VDD 1 0 5
VIN 2 0
.DC VIN 0 5 0. 1
.PLOT V(3) V(2)
.ALTER
.DEL LIB 'MOS.LIB' NORMAL
.TF V(3) VIN $DC small-signal transfer
function
.MACRO INV 1 2 3 $change data within
subcircuit def
M1 4 2 1 1 P 100U 100U $change channel
length,width,also topology
M2 4 2 0 0 N 6U 8U $change topology
R4 4 3 100 $add the new element
C3 3 0 10P $add the new element
.LIB 'MOS.LIB' SLOW $set slow model library
$.INC 'MOS2.DAT' $not allowed to be used
inside
$subcircuit allowed outside subcircuit
.EOM INV
.END
In Example 2, the .ALTER block
adds a resistor and capacitor network to the circuit. The network is connected to
the output of the inverter and a DC small-signal transfer function is
simulated.
.DATA Statement
Data-driven analysis allows the
user to modify any number of parameters, then perform an operating point, DC,
AC, or transient analysis using the new parameter values. An array of parameter
values can be either inline (in the simulation input file) or stored as an
external ASCII file. The .DATA statement associates a list of parameter names
with corresponding values in the array.
Syntax requires a .DATA statement
and an analysis statement that contains a DATA=dataname keyword.
Inline
.DATA Statement
Inline data is parameter data
listed in a .DATA statement block. It is called by the datanm parameter
in a .DC, .AC, or .TRAN analysis statement.
Syntax
.DATA datanm pnam1 <pnam2 pnam3 ... pnamxxx >
+ pval1<pval2 pval3 ... pvalxxx>
+ pval1’ <pval2’ pval3’ ... pvalxxx’>
.ENDDATA
Example
.TRAN 1n 100n SWEEP DATA=devinf
.AC DEC 10 1hz 10khz SWEEP DATA=devinf
.DC TEMP -55 125 10 SWEEP DATA=devinf
.DATA devinf width length thresh cap
+ 50u 30u 1.2v 1.2pf
+ 25u 15u 1.0v 0.8pf
+ 5u 2u 0.7v 0.6pf
+ ... ... ... ...
.ENDDATA
Star-Hspice performs the above
analyses for each set of parameter values defined in the .DATA statement. For
example, the program first takes the width=50u, length=30u, thresh=1.2v, and
cap=1.2pf parameters and performs .TRAN, .AC and .DC analyses. The analyses are
then repeated for width=25u, length=15u, thresh=1.0v, and cap=0.8pf, and again
for the values on each subsequent line in the .DATA block.
Example of DATA as the Inner Sweep
M1 1 2 3 0 N W=50u L=LN
VGS 2 0 0.0v
VBS 3 0 VBS
VDS 1 0 VDS
.PARAM VDS=0 VBS=0 L=1.0u
.DC DATA=vdot
.DATA vdot
VBS VDS L
0 0.1 1.5u
0 0.1 1.0u
0 0.1 0.8u
-1 0.1 1.0u
-2 0.1 1.0u
-3 0.1 1.0u
0 1.0 1.0u
0 5.0 1.0u
.ENDDATA
In the above example, a DC sweep
analysis is performed for each set of VBS, VDS, and L parameters in the “.DATA
vdot” block. That is, eight DC analyses are performed, one for each line of
parameter values in the .DATA block.
Example of DATA as an Outer Sweep
.PARAM W1=50u W2=50u L=1u CAP=0
.TRAN 1n 100n SWEEP DATA=d1
.DATA d1
W1 W2 L CAP
50u 40u 1.0u 1.2pf
25u 20u 0.8u 0.9pf
.ENDDATA
In the previous example, the
default start time for the .TRAN analysis is 0, the time increment is 1ns, and
the stop time is 100 ns. This results in transient analyses at every time value
from 0 to 100 ns in steps of 1 ns, using the first set of parameter values in
the “.DATA d1” block. Then the next set of parameter values is read, and
another 100 transient analyses are performed, sweeping time from 0 to 100 ns in
1 ns steps. The outer sweep is time, and the inner sweep varies the parameter values.
.TEMP Statement
The temperature of a circuit for
a Star-Hspice run is specified with the .TEMP statement or with the TEMP
parameter in the .DC, .AC, and .TRAN statements. The circuit simulation
temperature set by either of these is compared against the reference
temperature set by the TNOM control option. The difference between the circuit
simulation temperature and the reference temperature, TNOM, is used in
determining the derating factors for component values.
Syntax
.TEMP t1 <t2 <t3 ...>>
where:
t1 t2 … specifies temperatures, in °C, at which the circuit is to be simulated
Example
.TEMP 100
D1 N1 N2 DMOD DTEMP=30
D2 NA NC DMOD
R1 NP NN 100 DTEMP=-30
.MODEL DMOD D IS=1E-15 VJ=0.6 CJA=1.2E-13
CJP=1.3E-14 TREF=60.0
The circuit simulation temperature
is given from the .TEMP statement as 100°C. Since TNOM is not specified, it will default to 25°C. The temperature of the diode is given as 30°C above the circuit temperature by the DTEMP parameter; that is, D1temp
= 100°C + 30°C = 130°C. The diode D2 is simulated at
100°C. R1 is simulated at 70°C. Since TREF is specified at 60°C in the diode model statement, the diode model parameters given are
derated by 70°C (130°C - 60°C) for diode D1 and by 40°C (100°C - 60°C) for diode D2. The value of R1 is derated by 45°C (70°C - TNOM).
.OPTIONS Statement
·
Control options are set in .OPTIONS statements.
·
You can set any number of options in one .OPTIONS statement, and include
any number of .OPTIONS statements in a Star-Hspice input netlist file.
·
Generally, options default to 0 (off) when not assigned a value.
Syntax
.OPTIONS opt1 <opt2 opt3 ...>
Descriptions of General Control .OPTIONS Keywords
ACCT reports job accounting and runtime
statistics at the end of the output listing. Simulation efficiency is determined
by the ratio of output points to total iterations. Reporting is automatic
unless you disable it. Choices for ACCT are:
0 disables reporting
1 enables reporting (default)
2 enables reporting of MATRIX
statistics
BADCHR generates a warning when a
nonprintable character is found in an input file
BRIEF, NXX stops printback of the data file
until an .OPTIONS BRIEF=0 or the .END statement is encountered. It also resets
the options LIST, NODE and OPTS while setting NOMOD. BRIEF=1 enables printback.
NXX is the same as BRIEF.
CPTIME=x sets the maximum CPU time, in
seconds, allotted for this job. When the time allowed for the job exceeds
CPTIME, the results up to that point are printed or plotted and the job is
concluded.
INGOLD=x specifies the printout data
format. Use INGOLD=2 for SPICE compatibility. Default=0. Numeric output from
Star-Hspice is printed in one of three ways:
INGOLD = 0 Engineering format,
exponents are expressed as a single character:
1G=1e9
1X=1e6 1K=1e3 1M=1e-3
1U=1e-6 1N=1e-9 1P=1e-12 1F=1e-15
INGOLD = 1 Combined fixed and
exponential format (G Format). Fixed format for numbers between 0.1 and 999.
Exponential format for numbers greater than 999 or less than 0.1.
INGOLD = 2 Exclusively
exponential format (SPICE2G style). Exponential format generates constant
number sizes suitable for post-analysis tools.
Use .OPTIONS MEASDGT in
conjunction with INGOLD to control the output data format of .MEASURE results.
LIMPTS=x sets the total number of points
that you can print or plot in AC analysis. It is not necessary to set LIMPTS
for DC or transient analysis, as Star-Hspice spools the output file to
disk. Default=2001.
LIMTIM=x sets the amount of CPU time
reserved for generating prints and plots in case a CPU time limit (CPTIME=x) causes
termination. Default=2 (seconds). This default is normally sufficient time for
short printouts and plots.
LIST, VERIFY produces an element summary
listing of the input data to be printed. Calculates effective sizes of elements
and the key values. LIST is suppressed by BRIEF. VERIFY is an alias
for LIST.
MEASDGT=x used for formatting of the
.MEASURE statement output in both the listing file and the .MEASURE output
files (.ma0, .mt0, .ms0, and so on). The value of x is
typically between 1 and 7, although it can be set as high as 10. Default=4.0.
For example, if MEASDGT=5, numbers displayed by .MEASURE are displayed as:
five
decimal digits for numbers in scientific notation
five
digits to the right of the decimal for numbers
between
0.1 and 999
In the listing (.lis),
file, all .MEASURE output values are in scientific notation, so .OPTIONS
MEASDGT=5 results in five decimal digits.
Use MEASDGT in conjunction with
.OPTIONS INGOLD=x to control the output data format.
MEASOUT outputs .MEASURE statement values
and sweep parameters into an ASCII file for post-analysis processing by
AvanWaves or other analysis tools. The output file is named <design>.mt#,
where # is incremented for each .TEMP or .ALTER block.
NODE causes a node cross reference table to be
printed. NODE is suppressed by BRIEF. The table lists each node and all the
elements connected to it. The terminal of each element is indicated by a code,
separated from the element name with a colon (:).
For example, part of a cross
reference might look like:
1 M1:B D2:+ Q4:B
This line indicates that the bulk
of M1, the anode of D2, and the base of Q4 are all connected to node 1.
NOELCK no element check; bypasses
element checking to reduce preprocessing time for very large files.
NOMOD suppresses the printout of model
parameters
NOPAGE suppresses page ejects for title
headings
NOTOP suppresses topology check
resulting in increased speed for preprocessing very large files
NOWARN suppresses all warning messages
except those generated from statements in .ALTER blocks
NUMDGT=x sets the number of significant
digits printed for output variable values. The value of x is typically between
1 and 7, although it can be set as high as 10. Default=4.0. This option does
not affect the accuracy of the simulation.
OPTS prints the current settings
of all control options. If any of the default values of the options have been
changed, the OPTS option prints the values actually used for the simulation.
Suppressed by the BRIEF option.
POST=x enables storing of simulation
results for analysis using the AvanWaves graphical interface or other methods.
POST=2 saves the results in ASCII format. POST=1 saves the results in binary.
Set the POST option, and use the .PROBE statement to specify which data you
want saved. Default=1.
PROBE limits the post-analysis output
to just the variables designated in .PROBE, .PRINT, .PLOT, and .GRAPH
statements. By default, Star-Hspice outputs all voltages and power supply
currents in addition to variables listed in .PROBE/.PRINT/.PLOT/.GRAPH statements.
Use of PROBE significantly decreases the size of simulation output files.
SPICE makes Star-Hspice compatible with
Berkeley SPICE.
.INCLUDE Statement
Syntax
.INCLUDE ‘<filepath> filename’
.LIB Call and Definition Statements
You can place commonly used
commands, device models, subcircuit analysis and statements in library files by
using the .LIB call statement. As each .LIB call name is encountered in the
main data file, the corresponding entry is read in from the designated library
file. The entry is read in until an .ENDL statement is encountered. You also
can place a .LIB call statement in an .ALTER block.
.LIB
Library Call Statement
Syntax
.LIB ‘<filepath> filename’ entryname
or
.LIB libnumber entryname
entryname entry name for the section of the
library file to include. The first character of an entryname cannot be an
integer.
Example
.LIB 'MODELS' cmos1
.LIB
Library File Definition Statement
You can build libraries by using
the .LIB statement in a library file. For each
macro in a library, a library
definition statement (.LIB entryname) and an .ENDL
statement is used. The .LIB
statement begins the library macro, and the .ENDL
statement ends the library macro.
Syntax
.LIB entryname1
…
. $ ANY VALID
SET OF Star-Hspice STATEMENTS
…
.ENDL entryname1
.LIB entryname2
…
. $ ANY VALID
SET OF Star-Hspice STATEMENTS
…
.ENDL entryname2
.LIB entryname3
…
. $ ANY VALID
SET OF Star-Hspice STATEMENTS
.ENDL entryname3
Library Building Rules
1.
A library cannot contain .ALTER statements.
2.
A library may contain nested .LIB calls to itself or other libraries.
The depth of nested calls is only limited by the constraints of your system
configuration.
3.
A library cannot contain a call to a library of its own entry name
within the same library file.
4.
A library cannot contain the .END statement.
5.
.LIB statements within a file called with an .INCLUDE statement cannot
be changed by .ALTER processing.
.MODEL Statement
Syntax :
.MODEL mname type <VERSION=version_number>
<pname1=val1 pname2=val2 ...>
where:
mname model name reference. Elements
must refer to the model by this name.
type selects the model type, which must be one of
the following:
AMP
operational amplifier model
C
capacitor model
CORE
magnetic core model
D
diode model
L
magnetic core mutual inductor model
NJF
n-channel JFET model
NMOSn-channel
MOSFET model
NPN
npn BJT model
OPT
optimization model
PJF
p-channel JFET model
PLOT
hardcopy plot model for the .GRAPH statement
PMOS
p-channel MOSFET model
PNP
pnp BJT model
R
resistor model
pname1 ... parameter name. The model
parameter name assignment list (pname1) must be from the list of parameter
names for the appropriate model type. Default values are given in each model
section. The parameter assignment list can be enclosed in parentheses and each
assignment can be separated by either blanks or commas for legibility.
Continuation lines begin with a plus sign (+).
VERSION Star-Hspice version number, used
to allow portability of the BSIM (Level=13) and BSIM2 (Level=39) models between
Star-Hspice releases. Star-Hspice release numbers and the corresponding version
numbers are:
Star-Hspice
release Version number
9007B 9007.02
9007D 9007.04
92A 92.01
92B 92.02
93A 93.01
93A.02
93.02
95.3 95.3
96.1 96.1
The VERSION parameter is only
valid for Level 13 and Level 39 models, and in Star-Hspice releases starting
with Release H93A.02. Using the parameter with any other model or with a
release prior to H93A.02 results in a warning message, but the simulation
continues.
Example
.MODEL MOD1 NPN BF=50 IS=1E-13 VBF=50
AREA=2 PJ=3, N=1.05
.PROTECT Statement
Use the .PROTECT statement to
keep models and cell libraries private. The .PROTECT statement suppresses the
printout of the text from the list file, like the option BRIEF. The .UNPROTECT
command restores normal output functions. In addition, any elements and models
located between a .PROTECT and an .UNPROTECT statement inhibits the element and
model listing from the option LIST. Any nodes that are contained within the
.PROTECT and .UNPROTECT statements are not listed in the .OPTIONS NODE nodal
cross reference, and are not listed in the .OP operating point printout.
Syntax:
.PROTECT
.UNPROTECT Statement
The syntax is:
.UNPROTECT
Specifying
Simulation Output
Using Output Statements
Star-Hspice output statements are
contained in the input netlist file and include .PRINT, .PLOT, .GRAPH, .PROBE,
and .MEASURE.
Each statement specifies the
output variables and type of simulation result to be displayed—for example,
.DC, .AC, or .TRAN.
The .PRINT statement prints
numeric analysis results.
The .PLOT statement generates low
resolution printer plots in the output listing file.
The .GRAPH statement generates
high resolution plots for supported devices such as HP LaserJet and PostScript
printers without using AvanWaves.
The .PROBE statement (together
with .OPTION PROBE) allows output variables to be saved in all the interface
files with no additional output in the listing file.
The .MEASURE statement prints
numeric results of measured electrical specifications for specific analyses.
All output variables referenced
in .PRINT, .PLOT, .GRAPH, .PROBE, and .MEASURE statements are put into the
interface files for AvanWaves. AvanWaves allows high resolution, post
simulation, and interactive terminal or printer display of waveforms.
Nodal
Voltage Output
Syntax
V (n1<,n2>)
n1, n2 defines the nodes between which
the voltage difference (n1-n2) is to be printed or plotted. When n2 is omitted,
the voltage difference between n1 and ground (node 0) is given.
Examples
.PLOT TRAN I(VIN)
.PRINT DC I(X1.VSRC)
.PLOT DC I(XSUB.XSUBSUB.VY)
Current
Output: Element Branches
I1(R1)
This example specifies the
current through the first node of resistor R1.
I4(X1.M1)
The above example specifies the
current through the fourth node (the substrate node) of the MOSFET M1, which is
defined in subcircuit X1.
I2(Q1)
The last example specifies the
current through the second node (the base node) of the bipolar transistor Q1.
Power
Output
For power calculations,
Star-Hspice computes dissipated or stored power in each passive element (R, L,
C), and source (V, I, G, E, F, and H) by multiplying the voltage across an
element and its corresponding branch current. However, for semiconductor
devices, Star-Hspice calculates only the dissipated power. The power stored in
the device junction or parasitic capacitances is excluded from the device power
computation. Equations for calculating the power dissipated in different types
of devices are shown in the following sections.
Star-Hspice
also computes the total power dissipated in the circuit, which is the sum of
the power dissipated in the devices, resistors, independent current sources,
and all the dependent sources. For hierarchical designs, Star-Hspice computes
the power dissipation for each subcircuit as well.
Note: For the total power
(dissipated power + stored power), it is possible to add up the power of each
independent source (voltage and current sources).
Print or Plot Power
Output the instantaneous element
power and the total power dissipation using a .PRINT or .PLOT statement.
Syntax
.PRINT <DC | TRAN>
P(element_or_subcircuit_name)POWER
Power calculation is associated
only with transient and DC sweep analyses. The .MEASURE statement can be used
to compute the average, rms, minimum, maximum, and peak-to-peak value of the
power. The POWER keyword invokes the total power dissipation output.
Examples
.PRINT TRAN P(M1) P(VIN) P(CLOAD) POWER
.PRINT TRAN P(Q1) P(DIO) P(J10) POWER
.PRINT TRAN POWER $ Total transient
analysis power dissipation
.PLOT DC POWER P(IIN) P(RLOAD) P(R1)
.PLOT DC POWER P(V1) P(RLOAD) P(VS)
.PRINT TRAN P(Xf1) P(Xf1.Xh1)
.MEASURE Statement
Use the .MEASURE statement to
modify information and define the results of
successive simulations.
The .MEASURE statement prints
user-defined electrical specifications of a circuit and is used extensively in
optimization. The specifications include propagation, delay, rise time, fall
time, peak-to-peak voltage, minimum and maximum voltage over a specified
period, and a number of other user-defined variables. With the error mode and
GOAL parameter, .MEASURE is also used extensively for optimization of circuit
component values and curve fitting measured data to model parameters.
The .MEASURE statement has
several different formats, depending on the application. You can use it for
either DC, AC, or transient analysis.
Fundamental measurement modes
are:
·
Rise, fall, and delay
·
Average, RMS, min, max, peak-to-peak, and integral
·
Find-when
·
Equation evaluation
·
Derivative evaluation
·
Integral evaluation
·
Relative error
When a .MEASURE statement fails
to execute, Star-Hspice writes 0.0e0 in the .mt# file as the .MEASURE
result, and writes “FAILED” in the output listing file.
Examples
.MEASURE TRAN tdlay TRIG V(1) VAL=2.5
TD=10n RISE=2
+ TARG V(2) VAL=2.5 FALL=2
This example specifies that a
propagation delay measurement is taken between nodes 1 and 2 for a transient
analysis. The delay is measured from the second rising edge of the voltage at
node 1 to the second falling edge of node 2. The measurement is specified to
begin when the second rising voltage at node 1 is 2.5 V and to end when the
second falling voltage at node 2 reaches 2.5 V. The TD=10n parameter does not
allow the crossings to be counted until after 10 ns has elapsed. The results
are printed as tdlay=<value>.
.MEASURE TRAN riset TRIG I(Q1) VAL=0.5m
RISE=3
+ TARG I(Q1) VAL=4.5m RISE=3
.MEASURE pwidth TRIG AT=10n TARG V(IN)
VAL=2.5 CROSS=3
The last example uses the short
form of TRIG. AT=10n specifies that the time measurement is to begin at time
t=10 ns in the transient analysis. The TARG parameters specify that the time
measurement is to end when V(IN)=2.5 V on the third crossing. The variable pwidth
is the printed output variable.
Note: If the .TRAN statement is
used in conjunction with a .MEASURE statement, using a nonzero START time in
the .TRAN statement can result in incorrect .MEASURE results. Do not use
nonzero START times in .TRAN statements when .MEASURE is also being used.
Average,
RMS, MIN, MAX, and Peak-To-Peak Measurements
The average (AVE), RMS, MIN, MAX,
and peak-to-peak (PP) measurement modes report functions of the output variable
rather than the analysis value. Average calculates the area under the output
variable divided by the periods of interest. RMS takes the square root of the
area under the output variable square divided by the period of interest. MIN
reports the minimum value of the output function over the specified interval.
MAX reports the maximum value of the output function over the specified
interval. PP (peak-to-peak) reports the maximum value minus the minimum value
over the specified interval. Integral provides the integral of an output
variable over a specified period.
Examples
.MEAS TRAN avgval AVG V(10) FROM=10ns TO=55ns
The example above calculates the
average nodal voltage value for node 10 during the transient sweep from the
time 10 ns to 55 ns and prints out the result as “avgval”.
.MEAS TRAN MAXVAL MAX V(1,2) FROM=15ns TO=100ns
The example above finds the
maximum voltage difference between nodes 1 and 2 for the time period from 15 ns
to 100 ns.
.MEAS TRAN MINVAL MIN V(1,2) FROM=15ns TO=100ns
.MEAS TRAN P2PVAL PP I(M1) FROM=10ns TO=100ns
.MEAS TRAN charge INTEG I(cload) FROM=10ns TO=100ns
FIND
and WHEN Functions
The FIND and WHEN functions allow
any independent variables (time, frequency, parameter), any dependent variables
(voltage or current, for example), or the derivative of any dependent variables
to be measured when some specific event occurs. These measure statements are
useful in unity gain
frequency or phase measurements,
as well as for measuring the time, frequency, or any parameter value when two
signals cross each other, or when a signal crosses a constant value. The
measurement starts after a specified time delay, TD. It is possible to find a
specific event by setting RISE, FALL, or CROSS to a value (or parameter) or
LAST for last event. LAST is a reserved word and cannot be chosen as a
parameter name in the above measure statements.
Examples
.MEASURE AC output_voltage FIND VR(6) AT=100K
Measure the Vo at 100kHz.
.MEASURE AC output_voltage_db FIND
VdB(6) AT=100K
Measure the Vo(db) at
100kHz.
.MEASURE AC voltage_gain FIND
PAR='(VR(6)/VR(1))' AT=100K
Measure the V.GAIN at
100kHz.
.MEASURE AC voltage_gain_db FIND PAR='DB(VR(6)/VR(1))' AT=100K
Measure the V.GAIN(db) at
100kHz.
.MEASURE AC lower_3db_freq WHEN VM(6)='.707*ABS(OUTPUT_VOLTAGE)'
Find the lower 3dB
frequency.
.MEASURE AC upper_3db_freq WHEN VM(6)='.707*ABS(OUTPUT_VOLTAGE)' TD=1e5
Find the upper 3dB
frequency. The TD=1e5 parameter does not allow the crossings to be counted
until after 0.1MEGHZ has elapsed.
.MEASURE AC input_imp FIND
PAR='v(1)/i(vin)' AT=100K
Measure the input
impedance
Equation
Evaluation
Use this statement to evaluate an
equation that is a function of the results of previous .MEASURE statements. The
equation must not be a function of node voltages or branch currents.
Syntax
.MEASURE <DC|TRAN|AC> result PARAM=’equation’
+ <GOAL=val> <MINVAL=val>
DERIVATIVE
Function
The DERIVATIVE function provides
the derivative of an output variable at a given time or frequency or for any
sweep variable, depending on the type of analysis. It also provides the
derivative of a specified output variable when some specific event occurs.
Examples
The following example calculates
the derivative of V(out) at 25 ns:
.MEAS TRAN slewrate DERIV V(out) AT=25ns
The following example calculates
the derivative of v(1) when v(1) is equal to 0.9*vdd:
.MEAS TRAN slew DERIV v(1) WHEN v(1)=’0.90*vdd’
The following example calculates
the derivative of VP(output)/360.0 when the frequency is 10 kHz:
.MEAS AC delay DERIV ’VP(output)/360.0’ AT=10khz
INTEGRAL
Function
The INTEGRAL function provides
the integral of an output variable over a specified period.
Example
The following example calculates
the integral of I(cload) from t=10 ns to t = 100 ns:
.MEAS TRAN charge INTEG I(cload) FROM=10ns TO=100ns
Displaying Simulation
Results
.PRINT Statement
The .PRINT statement specifies
output variables for which values are printed. The maximum number of variables
in a single .PRINT statement is 32. You can use additional .PRINT statements
for more output variables.
To simplify parsing of the output
listings, a single “x” printed in the first column indicates the beginning of
the .PRINT output data, and a single “y” in the first column indicates the end
of the .PRINT output data.
Syntax
.PRINT antype ov1 <ov2 … ov32>
where
antype specifies the type of analysis
for outputs. Antype is one of the following types: DC, AC, TRAN, NOISE, or
DISTO.
ov1 …
specifies output
variables to be print. These are voltage, current, or element template
variables from a DC, AC, TRAN, NOISE, or DISTO analysis.
Examples
.PRINT TRAN V(4) I(VIN) PAR(`V(OUT)/V(IN)')
This example prints out the
results of a transient analysis for the nodal voltage named 4 and the current
through the voltage source named VIN. The ratio of the nodal voltage at node
“OUT” and node “IN” is also printed.
.PRINT AC VM(4,2) VR(7) VP(8,3) II(R1)
VM(4,2) specifies that the AC
magnitude of the voltage difference (or the difference of the voltage
magnitudes, depending on the value of the ACOUT option) between nodes 4 and 2
is printed. VR(7) specifies that the real part of the AC voltage between nodes
7 and ground is printed. VP(8,3) specifies that the phase of the voltage
difference between nodes 8 and 3 (or the difference of the phase of voltage at
node 8 and voltage at node 3 depending on the value of ACOUT options) is
printed. II(R1) specifies that the imaginary part of the current through R1 is
printed.
.PRINT AC ZIN YOUT(P) S11(DB) S12(M) Z11(R)
The above example specifies that
the magnitude of the input impedance, the phase of the output admittance, and
several S and Z parameters are to be printed. This statement would accompany a
network analysis using the .AC and .NET analysis statements.
.PRINT DC V(2) I(VSRC) V(23,17) I1(R1) I1(M1)
This example specifies that the
DC analysis results are printed for several different nodal voltages and
currents through the resistor named R1, the voltage source named VSRC, and the
drain- to-source current of the MOSFET named M1.
.PRINT NOISE INOISE
In this example the equivalent
input noise is printed.
.PRINT DISTO HD3 SIM2(DB)
This example prints the magnitude
of the third-order harmonic distortion and the decibel value of the
intermodulation distortion sum through the load resistor specified in the
.DISTO statement.
.PRINT AC INOISE ONOISE VM(OUT) HD3
In this statement, specifications
of NOISE, DISTO, and AC output variables are included on the same .PRINT
statements.
Print
Control Options
The number of output variables
printed on a single line of output is a function of the number of columns, set
by the option CO. Typical values are CO=80 for narrow printouts and CO=132 for
wide printouts. CO=80 is the default. The maximum number of output variables
allowed is 5 per 80-column output and 8 per 132-column output with twelve
characters per column. Star-Hspice automatically creates additional print
statements and tables for all output variables beyond the number specified by
the CO option. Variable values are printed in engineering notation by default:
F = 1e-15 M = 1e-3
P = 1e-12 K = 1e3
N = 1e-9 X = 1e6
U = 1e-6 G = 1e9
In contrast to the exponential
format, the engineering notation provides two to three extra significant digits
and aligns columns to facilitate comparison. To obtain output in exponential
format, specify INGOLD = 1 or 2 with an .OPTION statement.
INGOLD = 0 [Default]
Engineering Format:
1.234K
123M.
INGOLD = 1
G Format: (Fixed and Exponential)
1.234e+03
.123
INGOLD = 2
E Format: (Exponential SPICE)
1.234e+03
1.23e-01
.PLOT Statement
The .PLOT statement plots output
values of one or more variables in a selected analysis. Each .PLOT statement
defines the contents of one plot, which can have 1 to 32 output variables.
The number of .PLOT statements
you can specify for each type of analysis is unlimited.
Examples
In the following example, PAR
invokes the plot of the ratio of the collector current and the base current of
the transistor Q1.
.PLOT DC V(4) V(5) V(1) PAR(`I1(Q1)/I2(Q1)')
.PLOT TRAN V(17,5) (2,5) I(VIN) V(17) (1,9)
.PLOT AC VM(5) VM(31,24) VDB(5) VP(5) INOISE
The second of the two examples
above uses the VDB output variable to plot the AC analysis results of the node
named 5 in decibels. Also, NOISE results may be requested along with the other
variables in the AC plot.
.PLOT AC ZIN YOUT(P) S11(DB) S12(M) Z11(R)
.PLOT DISTO HD2 HD3(R) SIM2
.PLOT TRAN V(5,3) V(4) (0,5) V(7) (0,10)
.PLOT DC V(1) V(2) (0,0) V(3) V(4) (0,5)
In the last example above,
Star-Hspice sets the plot limits for V(1) and V(2), while 0 and 5 volts are
specified as the plot limits for V(3) and V(4).
.PROBE Statement
The .PROBE statement saves output
variables into the interface and graph data files. Star-Hspice usually saves
all voltages and supply currents in addition to the output variables. Set
.OPTION PROBE to save output variables only. Use the .PROBE statement to
specify which quantities are to be printed in the output listing.
Syntax
.PROBE antype ov1 ... <ov32>
Independent Source Element Statements
Examples
VX 1 0 5V
VB 2 0 DC=VCC
VH 3 6 DC=2 AC=1,90
IG 8 7 PL(1MA 0S 5MA 25MS)
VCC 10 0 VCC PWL 0 0 10NS VCC 15NS VCC 20NS 0
VIN 13 2 0.001 AC 1 SIN (0 1 1MEG)
ISRC 23 21 AC 0.333 45.0 SFFM (0 1 10K 5 1K)
VMEAS 12 9
DC
Sources
For a DC source, you can specify
the DC current or voltage in different ways:
V1 1 0 DC=5V
V1 1 0 5V
I1 1 0 DC=5mA
I1 1 0 5mA
The first two examples specify a
DC voltage source of 5 V connected between node 1 and ground. The third and
fourth examples specify a 5 mA DC current source between node 1 and ground. The
direction of current is from node 1 to ground.
AC
Sources
AC current and voltage sources
are impulse functions used for an AC analysis. Specify the magnitude and phase
of the impulse with the AC keyword.
V1 1 0 AC=10V,90
VIN 1 0 AC 10V 90
The above two examples specify an
AC voltage source with a magnitude of 10 V and a phase of 90 degrees. Specify
the frequency sweep range of the AC analysis in the .AC analysis statement. The
AC or frequency domain analysis provides the impulse response of the circuit.
Transient
Sources
For transient analysis, you can
specify the source as a function of time. The functions available are pulse,
exponential, damped sinusoidal, single frequency FM, and piecewise linear
function.
Mixed
Sources
Mixed sources specify source
values for more than one type of analysis. For example, you can specify a DC
source specified together with an AC source and transient source, all of which
are connected to the same nodes.
VIN 13 2 0.5 AC 1 SIN (0 1 1MEG)
The above example specifies a DC
source of 0.5 V, an AC source of 1 V, and a transient damped sinusoidal source,
each of which are connected between nodes 13 and 2. For DC analysis, the
program uses zero source value since the sinusoidal source is zero at time
zero.
Pulse Source Function
Syntax
PULSE <(>v1 v2 <td <tr <tf <pw
<per>>>>> <)>
Example 1
VIN 3 0 PULSE (-1 1 2NS 2NS 2NS 50NS 100NS)
vpulse 1 0 pulse( v1 v2 td tr tf pw per )
.param v1=1v v2=2v td=5ns tr=5ns tf=5ns pw=20ns per=50ns
The first example specifies a
pulse source connected between node 3 and node 0. The pulse has an output high
voltage of 1 V, an output low voltage of -1 V, a delay of 2 ns, a rise and fall
time of 2 ns, a high pulse width of 50 ns, and a period of 100 ns. The second
example specifies pulse value parameters in the .PARAM statement.
Sinusoidal Source Function
Syntax
SIN <(>vo va <freq <td <q<j>>>>
<)>
where:
vo voltage or current offset in volts or amps
va voltage or current amplitude in volts or
amps
freq frequency in Hz (default=1/TSTOP)
td delay in seconds (default=0.0)
q damping factor in 1/seconds (default=0.0)
j phase delay in degrees (default=0.0)
Example
VIN 3 0 SIN (0 1 100MEG 1NS 1e10)
The example specifies a damped
sinusoidal source connected between nodes 3 and 0. The waveform has a peak
value of 1 V, an offset of 0 V, a 100 MHz frequency, a time delay of 1 ns, a
damping factor of 1e10, and a phase delay of zero degrees.
Exponential Source Function
Syntax
EXP <(>v1 v2 <td1 <t1 <td2 <t2>>>>
<)>
where:
v1 initial value of voltage or current in volts
or amps
v2 pulsed value of voltage or current in volts
or amps
td1 rise delay time in seconds (default=0.0)
td2 fall delay time in seconds
(default=td1+TSTEP)
t1 rise time constant in seconds
(default=TSTEP)
t2 fall time constant in seconds
(default=TSTEP)
Example
VIN 3 0 EXP (-4 -1 2NS 30NS 60NS 40NS)
The above example describes an
exponential transient source that is connected between nodes 3 and 0. It has an
initial t=0 voltage of -4 V and a final voltage of -1 V. The waveform rises
exponentially from -4 V to -1 V with a time constant of 30 ns. At 60 ns it
starts dropping to -4 V again, with a time constant of 40 ns.
Piecewise Linear Source Function
Syntax
PWL <(>t1 v1 <t2 v2 t3 v3...>
<R <=repeat>> <TD=delay> <)>
where
v1 … specifies current or voltage values
t1 … specifies segment time values
R causes the function to repeat
repeat specifies the start point of the
waveform which is to be repeated
TD is keyword for time delay before piecewise
actually starts
delay specifies the length of time to
delay the piecewise linear function
Each pair of values (t1, v1)
specifies that the value of the source is v1 (in volts) at time t1.
Specify “R” to cause the function
to repeat. You can specify a value after this “R” to indicate the beginning of
the function to be repeated: the repeat time must equal a breakpoint in the
function. For example, if t1 = 1, t2 = 2, t3 = 3, and t4 = 4, “repeat” can be
equal to 1, 2, or 3.
Specify TD=val to cause a delay
at the beginning of the function. You can use TD with or without the repeat
function.
Example
V1 1 0 PWL (60N 0V, 120N 0V, 130N 5V, 170N
5V, 180N 0V, R 0N)
V2 2 0 PL 0V 60N, 0V 120N, 5V 130N, 5V 170N,
0V 180N, R 60N
Single-Frequency FM Source Function
Syntax
SFFM <(> vo va <fc <mdi <fs>>> <)>
where
vo output voltage or current offset, in volts
or amps
va output voltage or current amplitude, in
volts or amps
fc carrier frequency in Hz (default=1/TSTOP)
mdi modulation index (default=0.0)
fs signal frequency in Hz (default=1/TSTOP)
Amplitude Modulation Source Function
Syntax
AM (sa oc fm fc td)
where
sa signal amplitude (default=0.0)
fc carrier frequency (default=0.0)
fm modulation frequency (default=1/TSTOP)
oc offset constant (default=0.0)
td delay time before start of signal
(default=0.0)
Example
V1 1 0 AM(10 1 100 1K 1M)
V2 2 0 AM(2.5 4 100 1K 1M)
V3 3 0 AM(10 1 1K 100 1M)
Setting Initial Conditions for Transient Analysis
The first task Star-Hspice
performs for .OP, .DC sweep, .AC, and .TRAN analyses is to set the DC operating
point values for all nodes and sources. It does this either by calculating all
of the values or by applying values specified in .NODESET and .IC statements or
stored in an initial conditions file. If UIC is included in the .TRAN
statement, a transient analysis is started using node voltages specified in a
.IC statement.
Syntax
.IC V(node1) = val1 V(node2) = val2 ...
or
.DCVOLT V(node1) = val1 V(node2) = val2 ...
.NODESET V(node1)=val1 <V(node2)=val2 ...>
or
.NODESET node1 val1 <node2 val2>
Example
.IC V(11)=5 V(4)=-5 V(2)=2.2
.DCVOLT 11 5 4 -5 2 2.2
.NODESET initializes specified
nodal voltages for a DC operating point analysis. The .NODESET statement often
is used to correct convergence problems in DC analysis. Setting the nodes in
the circuit to values that are close to the actual DC operating point solution
enhances the convergence of the simulation. The simulator uses the NODESET
voltages for the first iteration only.
.NODESET V(5:SETX)=3.5V V(X1.X2.VINT)=1V
.NODESET V(12)=4.5 V(4)=2.23
.NODESET 12 4.5 4 2.23 1 1
Transient Analysis
Single-point analysis:
.TRAN var1 START=start1 STOP=stop1 STEP=incr1
or
.TRAN var1 START=<param_expr1> STOP=<param_expr2>
+ STEP=<param_expr3>
Double-point analysis:
.TRAN var1 START=start1 STOP=stop1 STEP=incr1
+ <SWEEP var2 type np start2 stop2>
or
.TRAN tincr1 tstop1 <tincr2 tstop2 ...tincrN tstopN>
+ <START=val> <UIC>
+ <SWEEP var pstart
+ pstop pincr>
Parameterized sweep:
.TRAN tincr1 tstop1 <tincr2 tstop2 ...tincrN tstopN>
+ <START=val> <UIC>
Data driven sweep:
.TRAN DATA=datanm
or
.TRAN var1 START=start1 STOP=stop1 STEP=incr1
+ <SWEEP DATA=datanm>
or
.TRAN DATA=datanm<SWEEP var pstart pstop pincr>
Examples
The following example performs
and prints the transient analysis every 1 ns for 100 ns.
.TRAN 1NS 100NS
The following example performs
the calculation every 0.1 ns for the first 25 ns, and then every 1 ns until 40
ns; the printing and plotting begin at 10 ns.
.TRAN .1NS 25NS 1NS 40NS START=10NS
The following example performs
the calculation every 10 ns for 1 ms; the initial DC operating point
calculation is bypassed, and the nodal voltages specified in the .IC statement
(or by IC parameters in element statements) are used to calculate initial
conditions.
.TRAN 10NS 1US UIC
The following example increases
the temperature by 10 °C through the range - 55 °C to 75 °C and performs transient analysis
for each temperature.
.TRAN 10NS 1US UIC SWEEP TEMP -55 75 10
The following performs an
analysis for each load parameter value at 1 pF, 5 pF, and 10 pF.
.TRAN 10NS 1US SWEEP load POI 3 1pf 5pf 10pf
The following example is a data
driven time sweep and allows a data file to be used as sweep input. If the
parameters in the data statement are controlling sources, they must be
referenced by a piecewise linear specification.
.TRAN data=dataname
.DC Statement
The .DC statement is used in DC
analysis to:
·
Sweep any parameter value
·
Sweep any source value
·
Sweep temperature range
·
Perform a DC Monte Carlo analysis (random sweep)
·
Perform a DC circuit optimization
·
Perform a DC model characterization
The format for the .DC statement
depends on the application in which it is used, as shown in the following
examples:
Syntax
Sweep or parameterized sweep:
.DC var1 START = start1 STOP = stop1 STEP =
incr1
or
.DC var1
START=<param_expr1> STOP=<param_expr2>
+ STEP=<param_expr3>
or
.DC var1 start1 stop1
incr1 <SWEEP var2 type np start2 stop2>
or
.DC var1 start1 stop1
incr1 <var2 start2 stop2 incr2 >
Data driven sweep:
.DC var1 type np start1 stop1 <SWEEP
DATA=datanm>
or
.DC DATA=datanm<SWEEP var2 start2 stop2
incr2>
or
.DC DATA=datanm
Examples
The following example causes the
value of the voltage source VIN to be swept from 0.25 volts to 5.0 volts in
increments of 0.25 volts.
.DC VIN 0.25 5.0 0.25
The following example invokes a
sweep of the drain to source voltage from 0 to 10 V in 0.5 V increments at VGS
values of 0, 1, 2, 3, 4, and 5 V.
.DC VDS 0 10 0.5 VGS 0 5 1
The following example asks for a
DC analysis of the circuit from -55°C to 125°C
in 10°C increments.
.DC TEMP -55 125 10
As a result of the following
script, a DC analysis is conducted at five temperatures: 0, 30, 50, 100 and 125°C.
.DC TEMP POI 5 0 30 50 100 125
In the following example, a DC
analysis is performed on the circuit at each temperature value, which results
from a linear temperature sweep from 25°C to 125°C (five points), sweeping a
resistor value called xval from 1 k to 10 k in 0.5 k increments.
.DC xval 1k 10k .5k SWEEP TEMP LIN 5 25 125
The example below specifies a
sweep of the value par1 from 1 k to 100 k by 10 points per decade.
.DC DATA=datanm SWEEP par1 DEC 10 1k 100k
The next example also requests a
DC analysis at specified parameters in the .DATA statement referenced by the
.DATA statement reference name datanm. Parameter par1 also is swept from 1k to
100k by 10 points per decade.
.DC par1 DEC 10 1k 100k SWEEP DATA=datanm
Using Other DC Analysis Statements
Star-Hspice provides the
following additional DC analysis statements. Each of these statements uses the
DC equivalent model of the circuit for its analysis functions. For .PZ,
capacitors and inductors are included in the equivalent circuit.
.OP specifies
the time or times at which an operating point is to be calculated.
.PZ performs
pole/zero analysis (.OP specification is not required)
.SENS
obtains the DC small-signal sensitivities of
specified output variables with respect to circuit parameters (.OP
specification is not required)
.TF
calculates the DC small-signal value of a
transfer function (the ratio of an output variable to an input source). An .OP
specification is not required.
AC Small Signal Analysis
The AC small signal analysis
computes AC output variables as a function of frequency.
The AC analysis statement permits
sweeping values for:
·
Frequency
·
Element
·
Temperature
·
Model parameter
·
Randomized distribution (Monte Carlo)
·
Optimization and AC design analysis
Additionally, as part of the
small signal analysis tools, Star-Hspice provides:
·
Noise analysis
·
Distortion analysis
·
Network analysis
·
Sampling noise
Syntax
Single/double sweep:
.AC type np fstart fstop
or
.AC type np fstart fstop <SWEEP var starstop
incr>
or
.AC type np fstart fstop <SWEEP var type
np start stop>
or
.AC var1 START= <param_expr1> STOP=
<param_expr2>
+ STEP = <param_expr3>
or
.AC var1 START = start1 STOP = stop1 STEP =
incr1
Parameterized sweep:
.AC type np fstart fstop <SWEEP
DATA=datanm>
or
.AC DATA=datanm
Examples
The following example performs a
frequency sweep by 10 points per decade from 1 kHz to 100 MHz.
.AC DEC 10 1K 100MEG
The next line calls for a 100
point frequency sweep from 1 Hz to 100 Hz.
.AC LIN 100 1 100HZ
The following example performs an
AC analysis for each value of cload, which results from a linear sweep of cload
between 1 pF and 10 pF (20 points), sweeping frequency by 10 points per decade
from 1 Hz to 10 kHz.
.AC DEC 10 1 10K SWEEP cload LIN 20 1pf 10pf
The following example performs an
AC analysis for each value of rx, 5 k and 15 k, sweeping frequency by 10 points
per decade from 1 Hz to 10 kHz.
.AC DEC 10 1 10K SWEEP rx n POI 2 5k 15k
The next example uses the DATA
statement to perform a series of AC analyses modifying more than one parameter.
The parameters are contained in the file datanm.
.AC DEC 10 1 10K SWEEP DATA=datanm
AC Analysis Output Variables
Output variables for AC analysis
include:
·
Voltage differences between specified nodes (or one specified node and
ground)
·
Current output for an independent voltage source
·
Element branch current
·
Impedance (Z), admittance (Y), hybrid (H), and scattering (S) parameters
·
Input and output impedance and admittance
Example
.PLOT AC VM(5) VDB(5) VP(5)
The above example plots the
magnitude of the AC voltage of node 5 using the output variable VM. The voltage
at node 5 is plotted with the VDB output variable. The phase of the nodal
voltage at node 5 is plotted with the VP output variable.
.PLOT AC IR(V1) IM(VN2B) IP(X1.X2.VSRC)
.PRINT AC IP1(Q5) IM1(Q5) IDB4(X1.M1)
.PRINT AC VT(10) VT(2,25) IT(RL)
.PLOT AC IT1(Q1) IT3(M15) IT(D1)
Note: Since there is
discontinuity in phase each 360°, the
same discontinuity is seen in TD, even though TD is continuous.
****** INTEG.SP ACTIVE INTEGRATOR ******
****** INPUT LISTING ******
V1 1 0 .5 AC 1
R1 1 2 2K
C1 2 3 5NF
E3 3 0 2 0 -1000.0
.AC DEC 15 1K 100K
.PLOT AC VT(3) (0,4U) VP(3)
.END
AC Network Output
Syntax
Xij (z), ZIN(z), ZOUT(z), YIN(z), YOUT(z)
where
X specifies Z for impedance, Y for admittance, H for hybrid, or S for
scattering parameters
ij i and j can be 1 or 2. They identify which matrix parameter is printed.
z output type (see Table 9-1:). If z is omitted, the magnitude of the
output variable is printed.
ZIN input
impedance. For a one port network ZIN, Z11, and H11 are the same
ZOUT output
impedance
YIN input
admittance. For a one-port network, YIN and Y11 are the same.
YOUT output
admittance
Examples
.PRINT AC Z11(R) Z12(R) Y21(I) Y22 S11 S11(DB)
.PRINT AC ZIN(R) ZIN(I) YOUT(M) YOUT(P) H11(M)
.PLOT AC S22(M) S22(P) S21(R) H21(P) H12(R)
Using Algebraic Expressions
You can replace any parameter
defined in the netlist by an algebraic expression with quoted strings. Then,
use these expressions as output variables in the .PLOT, .PRINT, and .GRAPH
statements. Using algebraic expressions can expand your options in the input
netlist file. Use algebraic expressions in the following ways:
·
Scaling or changing of element and model parameters
·
Parameterization:
.PARAM x=5
·
Algebra:
.PARAM x=’y+3’
·
Functions:
.PARAM rho(leff,weff)=’2+*leff*weff-2u’
·
Hierarchical subcircuit algebraic parameter passing
.subckt inv in out wp=10u wn=5u qbar_ic=vdd
.ic qbar=qbar_ic
...
.ends
·
Algebra in elements:
R1 1 0 r=’ABS(v(1)/i(m1))+10’
·
Algebra in .MEASURE statements:
.MEAS vmax MAX V(1)
.MEAS imax MAX I(q2)
.MEAS ivmax PARAM=’vmax*imax’
·
Algebra in output statements:
.PRINT conductance=PAR(‘i(m1)/v(22)’)
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